Team of 5 · 54 V PCB design and gigabit local networking · Fall 2026

Constraint

Construction engineers installing IP cameras, access points, and intercoms often need PoE power, power measurement, and a working link before building power or cabling exists.

Decision

Split the job: a four-layer PoE injector PCB (54 V / 3.3 V rails; built around the TPS23861) delivers power, while a Raspberry Pi 5 routes network traffic at Layer 3 and runs telemetry and the UI.

Evidence

In progress. Targets: ~200 Wh battery for about four hours of single-device testing, live voltage/current/power on OLED, PoE and link LEDs.

• Altium
• TPS23861
• Raspberry Pi 5
• Linux networking
• PoE
• OLED

Individual · Fall 2025

Constraint

Model how a caching processor generates and services instruction and data references across many cache shapes with one implementation.

Decision

Built a single cache_access path parameterized by block size, number of sets, and blocks per set, covering direct-mapped through fully associative.

Evidence

Validated hits, misses, dirty evictions, write-backs, and LRU replacement with an assembly-level test suite across configurations.

• C
• LC2K assembly
• Cache design
• LRU

Individual · Winter 2025

Constraint

Add, subtract, multiply, and divide 11-bit signed numbers on an FPGA using one shared datapath and a controller, with correct sign and overflow handling.

Decision

A finite-state machine drives a shared 11-bit adder/subtractor; multiplication uses a sequential Booth algorithm and division iterates on operand magnitudes.

Evidence

Verified arithmetic, state transitions, and corner cases (overflow, divide-by-zero) in ModelSim, then ran on DE2-115 switches, keys, HEX displays, and LEDs.

• Verilog
• ModelSim
• DE2-115 FPGA
• FSM design
• Booth's algorithm

Individual · 2026

Constraint

Build an 8-bit adder/accumulator at the transistor level that balances delay, area, and power under an 8 fF output load.

Decision

Used a 20-transistor full adder mixing pass-transistor logic, transmission gates, and CMOS inverters, with shared XOR/XNOR signals and alternating carry polarity.

Evidence

Verified with transient simulation and critical-path timing analysis; 16-transistor master-slave D flip-flops close the accumulator loop. Achieved a maximum simulated clock speed of 2.115 GHz.

• Cadence Virtuoso
• Transistor-level design
• Logical effort
• Spectre

Individual · 2026

Constraint

Classify dog breeds (binary and multiclass) from a limited dataset without overfitting.

Decision

Compared custom CNNs, transfer learning with different layer-freezing setups, and ViT inference under one pipeline with early stopping and checkpointing.

Evidence

Test AUROC of 0.832 with frozen pretrained convolutional layers; best custom CNN reached 0.7652.

• Python
• PyTorch
• CNNs
• Vision Transformers
• Transfer learning