DIGITAL DESIGN · FPGA

Sequential Four-Function Calculator

Parameterized FSM-controlled calculator in Verilog with Booth multiplication and iterative division.

Context: Digital logic design · University of Michigan
Role: Individual
When: Winter 2025

Verilog
ModelSim
DE2-115 FPGA
FSM design
Booth's algorithm

Constraint

Add, subtract, multiply, and divide 11-bit signed numbers on an FPGA using one shared datapath and a controller, with correct sign and overflow handling.

Decision

A finite-state machine drives a shared 11-bit adder/subtractor; multiplication uses a sequential Booth algorithm and division iterates on operand magnitudes.

Evidence

Verified arithmetic, state transitions, and corner cases (overflow, divide-by-zero) in ModelSim, then ran on DE2-115 switches, keys, HEX displays, and LEDs.

01 // Problem & constraints

Numbers are entered in signed-magnitude on board switches and results are shown in two's complement on 7-segment displays. Width is a parameter (W = 11 by default), so the datapath must scale.

02 // Module structure

▪FourFuncCalc: top-level datapath registers plus the FSM controller (states such as XInit, XClear, XLoadA, XResult, XAdd).
▪AddSub / FullAdder: shared ripple adder/subtractor used by every operation.
▪BoothMul: sequential Booth multiplier on a 2W-wide product with a $clog2(W) iteration counter.
▪SM2TC / TC2SM: signed-magnitude ↔ two's complement conversion.
▪Binary_to_7SEG and Clock_Div: display decoding and clock division for the board.

03 // Validation

▪ModelSim testbench covering each operation, chained operations, sign combinations, overflow, and divide-by-zero.
▪Integrated on the DE2-115 and checked by hand against expected results.

Code excerpt

FourFuncCalc.v · module interface

module FourFuncCalc
  #(parameter W = 11)              // Default bit width
  (
    input Clock,
    input Clear,                   // C button
    input Equals,                  // = button
    input Add, Subtract,
    input Multiply, Divide,
    input [W-1:0] Number,          // signed-magnitude on SW[W-1:0]
    output signed [W-1:0] Result,  // two's complement
    output Overflow
  );
  localparam WW = 2 * W;            // Booth product width
  localparam BoothIter = $clog2(W); // Booth counter width