VLSI · Digital IC design

8-Bit Dual-Mode Ripple-Carry Adder

Transistor-level adder/accumulator in Cadence Virtuoso, tuned for critical-path delay.

Context: VLSI Design · University of Michigan
Role: Individual
When: 2026

Cadence Virtuoso
Transistor-level design
Logical effort
Spectre

Constraint

Build an 8-bit adder/accumulator at the transistor level that balances delay, area, and power under an 8 fF output load.

Decision

Used a 20-transistor full adder mixing pass-transistor logic, transmission gates, and CMOS inverters, with shared XOR/XNOR signals and alternating carry polarity.

Evidence

Verified with transient simulation and critical-path timing analysis; 16-transistor master-slave D flip-flops close the accumulator loop. Achieved a maximum simulated clock speed of 2.115 GHz.

01 // Problem & constraints

The adder must work both as a plain adder and as an accumulator, driving an 8 fF load, while keeping the carry chain short.

02 // Key decisions

▪Shared XOR/XNOR control signals to cut logic depth.
▪Alternating carry-polarity stages to remove inverters from the carry chain.
▪Logical-effort-based buffer sizing for output stages.
▪16-transistor master-slave D flip-flops for the accumulator register.

03 // Validation

Transient simulations for functional correctness and critical-path timing analysis to confirm propagation delay.