Computer architecture

LC2K Cache Simulator

Configurable CPU cache integrated into an LC2K processor simulator.

Context: EECS 370: Introduction to Computer Organization · University of Michigan
Role: Individual
When: Fall 2025

C
LC2K assembly
Cache design
LRU

Constraint

Model how a caching processor generates and services instruction and data references across many cache shapes with one implementation.

Decision

Built a single cache_access path parameterized by block size, number of sets, and blocks per set, covering direct-mapped through fully associative.

Evidence

Validated hits, misses, dirty evictions, write-backs, and LRU replacement with an assembly-level test suite across configurations.

01 // Problem & constraints

A unified instruction/data cache sits between the behavioral LC2K simulator and memory. The simulator runs as ./simulator program.mc blockSizeInWords numberOfSets blocksPerSet, and all transfers to memory happen in whole blocks.

02 // Design

▪Write-back, allocate-on-write policy.
▪Associativity from 1 (direct-mapped) up to the number of blocks (fully associative).
▪Replacement prefers an invalid block, otherwise the least-recently-used block.
▪Cache size = blockSizeInWords × numberOfSets × blocksPerSet words; all parameters powers of two.

03 // Validation

▪Assembly-level tests that force hits, misses, dirty-block evictions, and memory write-backs.
▪Tracked cache statistics and memory transfers to check correctness and compare workloads.

Source is kept private under course academic-integrity rules; available to discuss in interviews.